The present invention disclosed herein relates to semiconductor devices, and more particularly, to semiconductor devices with three-dimensional structures.
With developments of semiconductor manufacturing technology, the demand for a high density memory has increased. Various methods have been suggested to satisfy the demand. One method is to provide a semiconductor device with a three-dimensional array structure. Technologies providing semiconductor devices with three-dimensional structures are disclosed, for example, in U.S. Pat. No. 5,835,396 titled “THREE-DIMENSIONAL READ-ONLY MEMORY,” U.S. Pat. No. 6,034,882 titled “VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION,” and U.S. Pat. No. 7,002,825 titled “WORD LINE ARRANGEMENT HAVING SEGMENTED WORD LINES.” The disclosures of each of the above-referenced patents are hereby incorporated herein in their entirety by reference.
A semiconductor device with a three-dimensional structure may include memory cell arrays formed in respective semiconductor layers. The semiconductor layers may include a silicon substrate and semiconductor layers that are sequentially stacked on the silicon substrate. The stacked semiconductor layers may be formed using selective epitaxial technology. An example of a semiconductor device with a stacked structure is a flash memory device. Since the flash memory device includes a plurality of word lines, a row decoder may be required to control the respective word lines.